ERSA News

Conference Programme

Invited Talks

  • Dr. Steven A. Guccione Dr. Steven A. Guccione, Cmpware, Inc., USA
    Multicore Devices: The New Generation of Reconfigurable Architectures

    Abstract:
    For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low cost and flexibility of a software solution combined with the high performance of fixed hardware. For a variety of practical reasons, much of the work in this area focused on commercial FPGA devices as the underlying hardware platform. Recently, several new designs ...     Read more ...

  • Prof. Marco Platzner Prof. Marco Platzner, Univ. of Paderborn, Germany
    The GOmputer Project: Accelerating GO with FPGAs

    Abstract:
    GO is a very popular board game, especially in the Asian world, with a reported number of more than 50 million players. In contrast to Chess, where programs are able to compete with human top players, GO programs are still rather weak. Game theory classifies GO and Chess as deterministic two-person zero-sum games with complete information, which allows to address them with game tree search techniques such as the alpha/beta ...     Read more ...

  • Prof. Jerry L. Trahan Prof. Jerry L. Trahan, Louisiana State Univ., USA
    Reconfigurable Mesh Techniques and Applications

    Abstract:
    The reconfigurable mesh (R-Mesh) is a computational model that captures many aspects of reconfigurable computation. It comprises an array of processing elements in which each processor has fixed external connections to its neighbors and configurable internal connections among its ports. Local configuration decisions collectively form buses for communication across the array. While the ability to change configurations at every step is ambitious,...     Read more ...

  • Greg Leeming Greg Leeming, Microelectronics Advanced Research Corporation, USA
    Ralph Cavin, Semiconductor Research Corporation, USA
    Kosmas Galatsis, UCLA, USA
    Cellular Automata Architectures

    Abstract:
    How will multicore processing evolve and what will be the dominant computer architecture of the future? As technology reaches the limits of CMOS and beyond, the physical realities of computing hardware might dictate the answer to these questions. The integration level for nanoscale electronic devices could eventually be in the range of 1010 to 1011 devices per square centimeter. At this level long interconnects represent a significant challenge to operation ...     Read more ...

  • Prof. TBA Prof. Parag K. Lala, Texas A&M Univ.-Texarkana, USA
    On FPGA Design With Self-Checking And Fault Tolerance Capability

    Abstract:
    This paper discusses the work done by the author in the area of self-checking and faulttolerant FPGA design. It also proposes an FPGA architecture that is composed of functional cells with built in error correction capability. A functional cell in the proposed architecture can be used to implement logic functions as well as to route signals to other functional cells. It is composed of three units: a logic block,...     Read more ...

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