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ERSA’09 Invited Talk

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The 2nd Generation Japanese Dynamically Reconfigurable Processors

Prof. Hideharu Amano

Speaker: Prof. Hideharu Amano, Keio University, Japan

Abstract:

Dynamically Reconfigurable Processors have been started to be utilized as an off-load engine for various types of System-on-Chips (SoCs) in digital appliances. In order to achieve better area- and power-efficiency compared with traditional field-programmable devices such as FPGAs, they incorporate the following properties; (1) a simple coarse grained processor consisting of an ALU, a data manipulator, a register file and other functional modules is used as a primitive processing element (PE) of an array, and (2) dynamic reconfiguration of the PE array which enables time-multiplexed execution is introduced. Some of them provide multiple sets of configuration data called hardware contexts and switch them in one or a few clock cycles, and others can change their configuration in several micro seconds.

Based on the experience of the first generation products; recent 2nd generation dynamically reconfigurable processors; NEC electronics' STP-engine, IPFlex's DAPDNA-IMX, Toshiba's FlexSword, Hitachi's FE-GA and SANYO's reconfigurable car turner; are specialized for a specific field of applications, and adopt multi-core structure consisting of multiple small PE arrays. Especially in Japan, some of them are embedded in real commercial products: professional video camcorders, a portable game machine and multifunctional printers.


BIO:

Hideharu Amano received the Ph.D degree from Keio University in 1986. He is currently a professor in the Dept. of Information and Computer Science, Keio University. His research interests include the area of parallel processing and reconfigurable systems.


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