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ERSA’09 Invited Talk

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FPGA prototyping approach for the validation of efficient iterative receivers in digital communication systems

Prof. Christophe Jego

Speaker: Prof. Christophe Jego, ENST Bretagne, France

Abstract:

The turbo principle is a general way of processing data in receivers so that no information is wasted. This technique corresponds to an iterative exchange of soft information between different blocks in a communications receiver in order to improve overall system performance. It has opened up a new way of thinking in the construction of communication algorithms. This method was introduced in a system of error control for data transmission in 1993, called turbo code. This family of Forward Error Codes (FEC) consists of two key design innovations: concatenated encoding and iterative decoding. Soft Input Soft Output (SISO) decoders are used in an iterative decoding process. A SISO decoder both receives soft decision data and produces soft decision output. This general concept has been extended to product code family in 1994. Moreover, the iterative process embodied in the message-passing decoding algorithm has received great interest recently due to the rediscovery of low density parity check (LDPC) codes, a class of linear block codes defined by a sparse parity check matrix. It is now widely recognized as a very powerful concept in digital communication systems, with applications that go beyond the practical decoding of FEC. The turbo principle has been extended into new receiver topologies such as turbo detection, turbo equalization, turbo-coded modulation, turbo MIMO, etc. In the case of transmission systems with interference, such an iterative receiver, known as turbo equalizer or turbo detector, achieves significant gains in BER performance, compared with a non-iterative scheme. However, the design of high throughput, low complexity and low latency architectures for a receiver that contains an iterative process is a great challenge. In this context, we apply an Algorithm-Architecture-Matching approach for the design and the implementation of architectures dedicated to receivers that include an iterative exchange of soft information between different blocks. Performance of the proposed receivers is studied using real-time FPGA prototyping boards.

A first study consists in designing flexible architectures and highly parallel architectures for the family of product codes. Two of the proposed architectural solutions are designed for programmable targets (Xilinx FPGA) and implemented onto prototyping boards. Both prototypes demonstrate that above Gb/s throughputs are reachable onto programmable devices such as FPGA. Another one is able to decode BCH and Reed-Solomon product codes with single or double correction power thanks to a flexible architecture. In reconfigurable systems, one of the most difficult aspects is the design of the controller, which supervises the reconfiguration. In our design, the control task is achieved by a Nios embedded processor. A real-time prototype based on the Stratix EP1S40 device was finally done. A second study is about the design of an iterative receiver for linearly precoded MIMO systems. Indeed, iterative receivers have been demonstrated to deal efficiently with the presence of co-antenna interference. However their complexity is often seen as a brake for their use in real-time systems. The iterative receiver is composed of two main elements: an MMSE equalizer and a 64-state convolutional decoder which exchange soft information through an interleaving scheme. Each block of the architecture was designed to reach a trade off between complexity and error rate performance. Our objective is to validate the potential of iterative receiver as practical and competitive solution for linearly precoded MIMO systems. In order to demonstrate the feasibility of the turbo receiver design, a real-time implementation onto FPGA device has been investigated.


BIO:

Christophe JEGO was born in Auray, France, in 1973. He received the M.S. and Ph.D. degrees from the Université Rennes 1, Rennes, France, in 1996 and 2000, respectively. He joined the electronic engineering department of TELECOM Bretagne as a full-Time Associate Professor in 2001. TELECOM Bretagne (formerly ENST Bretagne) is one of the most prestigious graduate engineering schools ("Grandes Ecoles") in France. From September 2006 to June 2007, he was a visiting professor in the Department of Electrical and Computer Engineering at McGill University, Montreal, Canada. His research activities are concerned with Algorithm-Architecture-Matching approach for iterative processing (turbo principle) in digital communications systems. The turbo principle is a general way of processing data in receivers so that no information is wasted. His work is about all aspects of mapping algorithms to architectures to implementations.


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