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ERSA’09 Invited Talk

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How constrains programming can help you in the generation of optimized application specific reconfigurable processor extensions

Prof. Christophe Wolinski

Speaker: Prof. Christophe Wolinski, University of Rennes I, France
Prof. Krzysztof Kuchcinski, Lund University, Sweden
Kevin Martin, University of Rennes I, France
Erwan Raffin, Thomson Corporate Research, Rennes, France
Francois Charo, University of Rennes I, France

Abstract:

We present different tasks from the generic design flow that is used to identify and select computational patterns as well as map applications and schedule them on processors with extensions implementing these patterns. The distinctive feature of our approach is that all design tasks are completely specified and solved using constraints programming with specially developed graph constraints. Therefore our approach is very flexible and makes possible to easily include new design constraints. Our design flow automatically creates functionally reconfigurable processor extensions implementing different architectural models. The selected processor extensions are accessed from processors using specialized instructions. These instructions correspond to computational patterns identified as most frequently occurring or other interesting patterns in the application graph. The architectural and technological constraints imposed by target processors and FPGA devices can be considered during the identification process. Typical constraints include the number of inputs and outputs, the number of operators, and the critical path delay of patterns. Therefore the identified patterns can be well tailored to target processors. The selected computational patterns are then merged into reconfigurable cells under design constraints optimizing different design aspects. Our methods can handle both time-constrained and resource-constrained application scheduling that provides opportunity for exploration of the design space. The results obtained for real-life applications are presented.


BIO: Prof. Christophe Wolinski

Christophe Wolinski is a professor at the University of Rennes I (France). He has an MSc (1976) and PhD (1982) from the Warsaw University of Technology (Poland) and D.Sc. (2000) from the University of Rennes I (France). He was assistant professor in the Warsaw University of Technology (1982-1986). In 1986, he joined the University of Rennes I (France). He was a visiting staff member at Los Alamos National Laboratory (USA) (2001-2003). He currently works at the University of Rennes I (France) and he is a member of the INRIA CAIRN team in the IRISA laboratory of Rennes. He was a scientific advisor for many companies. He is a program committee member for leading conferences on electronic design and design automation and a general chair for some of them. His research interests include real time systems, digital signal processing architectures, high level synthesis, re-configurable computing systems and system modeling and optimization. His recent works concern the generation of automatic reconfigurable processor extensions and the optimized mapping/scheduling of applications on application specific reconfigurable architectures.


Prof. Krzysztof Kuchcinski

Krzysztof Kuchcinski is a professor of Computer Science at the Department of Computer Science, Lund University, Sweden. He received the MSc (1977) and PhD (1984) from Gdansk University of Technology, Poland. In 1986, he joined Linköping University (Sweden) where he served as Director of Computer-Aided Design Laboratory (CADLAB) and he become the professor of computer systems in 1999. He currently works at Lund University where he is the Head of the Department of Computer Science and leads the Embedded Systems Design Laboratory (ESDlab). His research interests concentrate on design methods for embedded systems at the architectural level, and in particular, on embedded system analysis and synthesis, reconfigurable computing, and design modeling and optimization. Prof. Kuchcinski is one of two main authors of the JaCoP finite domain constraint programming solver specially developed to solve embedded system design problems. He is also a co-author of the book on "System Synthesis with VHDL", the editor-in-chief of the Elsevier Journal on Embedded Hardware Design and a program committee member for several leading conferences on electronic design and design automation.


Kevin Martin

Kevin Martin,


Erwan Raffin

Erwan Raffin,


Francois Charo

Francois Charo,


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