WORLDCOMP’09 Congress Keynote
Univ. of Southern California, USA
Algorithm Design for Reconfigurable Computing Systems
Reconfigurable devices and systems have evolved dramatically over the past decade. Recently, several state-of-the-art high end platforms have incorporated FPGAs (Field Programmable Gate Arrays) for application acceleration. This talk explores algorithmic optimizations for accelerating a wide variety of applications including Gigabit rate deep packet inspection, high speed packet classification in Internet routers, embedded computing and scientific computing. We illustrate the performance improvements...
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Our keynotes from previous years:
VP of Engineering, ElementCXI, Milpitas, CA, USA
Dimensions in Reconfigurable Computing:
A New Wave In Electronic System Designs
ElementCXI is the finalist in EE Times 2008 ACE awards as "Most Promising Technology"
When will Reconfigurable Computing reach its promise of ubiquitous transparent computing in everyday electronic system designs? What is the nature and form of these systems in near term deployment and in long term requirements? More importantly - what does reconfigurable computing mean to the system developer, engineer and researcher and, what does it mean in terms of development needs? While this may seem straight-forward to someone experienced in this field; recent announcements in grid computing, multi-core processing, and FPGAs appear to serve to many of the key tenets of Reconfigurable Computing with massive computing throughput, low power operation, and dynamic operation contexts. But, do they?
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Technology Evangelist, Tensilica, Inc., USA
Challenges in Consumer Electronics for 21st Century
2007 Read more ...
President and CEO, Tensilica, Inc., USA
The Reinvention of the Microprocessor
2006 Read more ...
Independent Consultant, USA
Where Intel's Microprocessor Architecture is Going
Stanford University, USA
Computer Architecture, the road ahead
Gilder Technology Report, USA
The Rise Of Reconfigurable Systems