ERSA’11 Home

ERSA’11 PROGRAMME

Monday, 18 July 2011

WORLDCOMP’11 OPENING SESSION
Time	Location	Type	Presentation
08:30 - 08:45am:	The Monte Carlo Theater	W'COMP Opening	Prof. Hamid R. Arabnia, WORLDCOMP General Chair
08:50 - 09:45am:	The Monte Carlo Theater	ERSA/ W'COMP KEYNOTE	How Engineering Mathematics can Improve Software, Prof. David Lorge Parnas Middle Road Software, Inc, Canada
09:50 - 10:45am:	The Monte Carlo Theater	ERSA/ W'COMP KEYNOTE	The Nature of Cyber Security, Prof. Eugene Howard Spafford, Purdue University, USA
10:50 - 11:45am:	The Monte Carlo Theater	W'COMP KEYNOTE	Changing Lives around the World: the Power of Technology, Dr. Sandeep Chatterjee, Ph.D. Vice President & Chief Technology Officer, SourceTrace Systems, Inc., USA
11:45am - 12:00pm:	The Monte Carlo Theater	W'COMP KEYNOTE	European Research Council - Financing Frontier Research in Computer Science, Dr. Yiannis Sagias, Ph.D., Project adviser, European Research Council Executive Agency (ERCEA)
12:00 - 01:00pm:	N/A	LUNCH	On Your Own

ERSA’11 Time Schedule
Time	Location	Type	Presentation
01:00 - 01:10pm:	Gold Room	ERSA Opening	Dr Toomas P. Plaks, ERSA Chair
01:10 - 05:00pm:	Gold Room	REGULAR SESSION	ADAPTIVE AND RECONFIGURABLE HARDWARE Chair: Prof. David Andrews, University of Arkansas, USA
01:10 - 01:20pm:	Gold Room	SESSION Intro	Intro by Session Chair Prof. David Andrews
01:20 - 01:40pm:	Gold Room	Invited	Design Flows and Run Time Systems for Heterogeneous Multiprocessor Systems on Programmable Chips (MPSOPCS), David Andrews, University of Arkansas, USA
01:40 - 02:00pm:	Gold Room	Invited	Can Run-time Reconfigurable Hardware be more Accessible? Jim Tørresen and Dirk Koch, University of Oslo, Norway
02:00 - 02:20pm:	Gold Room	Invited	SAHA: A Self-Adaptive Hardware-Software System Architecture for Ubiquitous Computing Applications, Pao-Ann Hsiung and Chun-Hsian Huang, National Chung Cheng University, Taiwan, R.O.C.
02:20 - 02:40pm:	Gold Room	Regular	Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors, Y. Ohbayashi, H. M. Waidyasooriya, M. Hariyama, Kameyama, Tohoku University, Japan
02:40 - 03:00pm:	Gold Room	Regular	Placement and Routing Algorithm for Pipeline Architecture, Mayuko Koezuka, Akira Kuroda, Kenji Funaoka, Hidenori Matsuzaki, Takashi Yoshikawa and Shigehiro Asano, Toshiba Corporation, Japan
03:00 - 03:20pm:		Coffee Break
03:20 - 03:40pm:	Gold Room	Regular	Dynamic reconfiguration on a dynamically reconfigurable vision-chip architecture, Amarjargal Gundjalam and Minoru Watanabe, Shizuoka University, Japan
03:40 - 04:00pm:	Gold Room	Regular	Evaluating Expression Trees in Hardware, Lars Middendorf, Christophe Bobda, University of Potsdam, Germany, **University of Arkansas, USA
04:00 - 04:20pm:	Gold Room	Regular	A New Hardware/Software Partitioning Methodology Combining Search Space Smoothing and Discrete Particle Swarm Optimization, Yu Chen, Pranav Vaidya, Jaehwan John Lee, Chandima Hewa Nadungodage, Yuni Xia, Renfa Li, Qiang Wu, Indiana University-Purdue University Indianapolis, U.S., **Hunan University Hunan, P.R. China
04:20 - 04:40pm:	Gold Room	Regular	A Scalable FPGA Vehicle Monitoring Architecture, Francis Bowen, Jaehwan John Lee, Yingzi Du, Indiana University-Purdue University, Indianapolis, U.S.
04:40 - 05:00pm:	Gold Room	Regular	Rapid Implementation of Floating-Point Computations Using Phase-Coherent Dynamically Configurable Pipelines David K. Rutishauser, Robert L. Shuler Avionic Systems Division, NASA Johnson Space Center, USA
05:00 - 05:30pm:		FREE SLOT
05:30 - 07:00pm:	Gold Room	TUTORIAL	A Run-Time Evolvable Hardware, Prof. Jim Tørresen, University of Oslo, Norway
07:00 - 08:30pm:		FREE SLOT
09:10 - 11:30pm:	Ballrooms 1-5	DINNER	CONFERENCE RECEPTION DINNER / SOCIAL